Transmission of data from a processing engine to a display device for subsequent presentation or display is known. For example, data may be transmitted from a video graphics controller, or video graphics processing engine, to an LCD (liquid crystal diode) display panel for subsequent display. Because of the digital nature of the data (e.g., binary signal switching between zero volts and the voltage supply), electromagnetic interference (EMI) is generated. For relatively small amounts of data transmissions, the resulting EMI is practically negligible (i.e., the EMI does not adversely affect circuit operation and is below EMI levels established by regulatory agencies such as the Federal Communications Commission (FCC)).
As the LCD display increases in size and/or the complexity of the displayed data increases, the amount of data conveyed from the video graphics circuit is similarly increased. Not surprisingly, the generated EMI increases correspondingly to the increase in data transmission. In fact, in many high volume data transmissions, the EMI generated exceeds FCC regulations. Systems, such as computers, that employee the high volume data transmissions that are not FCC compliant are, as a result, not marketable.
To combat the EMI problem created from high volume data transmissions, a standard low voltage differential signaling (LVDS) for interface circuits has been developed. In particular, TIA/EIA-644 LVDS standard governs LVDS transmissions. The TIA/EIA-644 standard provides general specifications as to the accessible operating criteria for low voltage differential signaling. Such specifications require that signal transmissions be done using differential signaling, which substantially reduces the effects of the EMI generated by having the differential signals transmitted over a twisted wire pair, or at least an equivalent transmission medium. The specifications also dictate the signaling levels, such as the signal magnitude and the DC offset voltage. While the TIA/EIA-644 standard provides operational parameters, it does not provide information as to specific circuit implementations.
One TIE/EIA-644 standard compliance circuit has been developed by National Semiconductor (Part No. DS90CR581). In this circuit, National uses two pairs of cascaded transistors, which are switched as a full bridge inverter. The interconnecting nodes of each pair of cascaded transistors provide the differential output, while the ends of each of the pair of cascaded transistors are coupled to a current source and circuit return, respectively. The DC offset as specified in the standard is achieved by controlling the conductive impedance of the transistors to produce a voltage divider circuit. While this circuit works well in many applications, controlling the conductive impedance may provide manufacturing difficulties and, if the conductive impedance drifts due to manufacturing differences or gate drive circuits, the resulting differential output may not have the specified DC offset.
Therefore, a need exists for a method and apparatus that is TIA/EIA-644 compliant and is not heavily dependent on conductive impedances of the transistors and provides a low common mode impedance.